Finish simple_expressions example
This commit is contained in:
parent
be71569f56
commit
f8eb36a4e0
0
simple_examples/keypress.pas
Normal file
0
simple_examples/keypress.pas
Normal file
@ -9,9 +9,14 @@ var
|
|||||||
begin
|
begin
|
||||||
WriteLn('Initial value of b is ', b, '; initial value of c is ', c, sLineBreak);
|
WriteLn('Initial value of b is ', b, '; initial value of c is ', c, sLineBreak);
|
||||||
b := b shr 1; // >> shift right
|
b := b shr 1; // >> shift right
|
||||||
c := shl 4; // << shift left
|
c := c shl 4; // << shift left
|
||||||
WriteLn('After b shr 1, b is ', b, '; after c shl 4, c is ', c, sLineBreak);
|
WriteLn('After b shr 1, b is ', b, '; after c shl 4, c is ', c, sLineBreak);
|
||||||
WriteLn('c xor b = ',c xor b, '; c and b = ', c and b, '; c or b,'
|
WriteLn('c xor b = ',c xor b, '; c and b = ', c and b, '; c or b = ', c or b);
|
||||||
|
WriteLn('not c is ', not c, '; not b is ', not b);
|
||||||
|
WriteLn;
|
||||||
|
WriteLn('c > b is ', c > b, '; c < b is ', c < b, '; c <> b is ', c <> b, '; c = b is ', c = b);
|
||||||
|
WriteLn;
|
||||||
|
WriteLn('c div b is ', c div b, '; c mod b is ', c mod b);
|
||||||
{$IFDEF WINDOWS}
|
{$IFDEF WINDOWS}
|
||||||
ReadLn;
|
ReadLn;
|
||||||
{$ENDIF}
|
{$ENDIF}
|
||||||
|
Loading…
Reference in New Issue
Block a user